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cy8c21123, cy8c21223, CY8C21323 psoc ? mixed signal array cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-12022 rev. *h revised october 22, 2008 features powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? low power at high speed ? 2.4v to 5.25v operating voltage ? operating voltages down to 1.0v using on-chip switch mode pump (smp) ? industrial temperature range: -40c to +85c advanced peripherals (psoc blocks) ? four analog type ?e? psoc blocks provide: ? two comparators with dac refs ? single or dual 8-bit 8:1 adc ? four digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? crc and prs modules ? full duplex uart, spi ? master or slave ? connectable to all gpio pins ? complex peripherals by combining blocks flexible on-chip memory ? 4k flash program storage 50,000 erase/write cycles ? 256 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer ? ) ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128 bytes trace memory precision, programmable clocking ? internal 2.5% 24/48 mhz oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 25 ma drive on all gpio ? pull up, pull down, high z, strong, or open drain drive modes on all gpio ? up to eight analog inputs on gpio ? configurable interrupt on all gpio additional system resources ? i 2 c? master, slave and multimaster to 400 khz ? watchdog and sleep timers ? user configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference digital system sram system bus inter r upt controller sleep and watchdog clock sources (includes imo and ilo) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flas h i2c internal voltage ref . digital cloc ks por and lvd system resets system resources analog system analog ref . po r t 1 po r t 0 digital psoc block array analog psoc block array sw itch mode pu mp logic block diagram [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 2 of 37 psoc ? functional overview the psoc ? family consists of many mixed signal array with on-chip controller devices. these devices are designed to replace multiple traditional m cu-based system components with a low cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture allows the user to create customized peripheral configurations, to match the requirements of each individua l application. additionally, a fast cpu, flash program memory, sram data memory, and configurable io are included in a range of convenient pinouts. the psoc architecture, as shown in figure 1 , consists of four main areas: the core, the system resources, the digital system, and the analog system . configurable global bus resources allow the combining of all device resources into a complete custom system. each pso c device includes four digital blocks. depending on the psoc package, up to two analog comparators and up to 16 general purpose io (gpio) are also included. the gpio provide access to the global digital and analog interconnects. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard architecture microprocessor. system resources provide additional capability, such as digital clocks to increase the flexibili ty of the psoc mixed-signal arrays, i2c functionality for implementing an i2c master, slave, multi- master, an internal voltage refe rence that provides an absolute value of 1.3v to a number of psoc subsystems, a switch mode pump (smp) that generates normal operating voltages off a single battery cell, and various system resets supported by the m8c. the digital system consists of an array of digital psoc blocks, which can be configured into any number of digital peripherals. the digital blocks can be connected to the gpio through a series of global bus that can route any signal to any pin. this frees designs from the constraints of a fixed peripheral controller. the analog system consists of four analog psoc blocks, supporting comparators and analog-to-digital conversion up to 8 bits in precision. digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit per ipherals, which are called user module references. digital peripheral configurations include: pwms (8 to 32 bit) pwms with dead band (8 to 32 bit) counters (8 to 32 bit) timers (8 to 32 bit) uart 8 bit with selectable parity (up to four) spi master and slave i2c slave, master, multimaster (one available as a system resource) cyclical redundancy checker/generator (8 to 32 bit) irda (up to four) pseudo random sequence generators (8 to 32 bit) the digital blocks can be connected to any gpio through a series of global bus that can route any signal to any pin. the busses also allow for signal multiplexing and performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in ro ws of four, where the number of blocks varies by psoc device fam ily. this provides an optimum choice of system resources fo r your application. family resources are shown in ta b l e 1 on page 3. figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 ro w 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 1 port 0 [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 3 of 37 analog system the analog system consists of f our configurable blocks to allow creation of complex analog signal flows. analog peripherals are very flexible and may be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (single or dual, with 8-bit resolution) pin-to-pin comparators (one) single-ended comparators (up to 2) with absolute (1.3v) reference or 8-bit dac reference 1.3v reference (as a system resource) in most psoc devices, analog blo cks are provided in columns of three, which includes one ct (continuous time) and two sc (switched capacitor) blocks. the cy8c21x23 devices provide limited functionality type ?e? analog blocks. each column contains one ct block and one sc block. the number of blocks is on the device family which is detailed in ta b l e 1 . figure 2. cy8c21x23 anal og system block diagram additional system resources system resources, some of which listed in the previous sections, provide additional capability useful to complete systems. additional resources include a switch mode pump, low voltage detection, and power on reset. brief statements describing the merits of ea ch system resource follow. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i2c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch mode pump (smp) generates normal operating voltages from a single 1.2v battery cell, providing a low cost boost converter. psoc device characteristics depending on your psoc device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. table 1 lists the resources available for specific psoc device groups. the psoc de vice covered by this data sheet is highlighted. ac ol 1m u x ace00 ace01 array array input configuration aci0[1:0] aci1[1:0] ase10 ase11 table 1. psoc device characteristics psoc part number digital io digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 up to 64 4 16 12 4 4 12 2k 32k cy8c27x43 up to 44 2 8 12 4 4 12 256 bytes 16k cy8c24x94 56 1 4 48 2 2 6 1k 16k cy8c24x23a up to 24 1 4 12 2 2 6 256 bytes 4k cy8c21x34 up to 28 1428024 a a. limited analog functionality . 512 bytes 8k cy8c21x23 16 1 4 8 0 2 4 a 256 bytes 4k cy8c20x34 up to 28 0 0 28 0 0 3 b b. two analog blocks and one capsense. 512 bytes 8k [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 4 of 37 getting started the quickest path to understanding psoc silicon is by reading this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an overview of the psoc integrated circuit and pr esents specific pin, register, and electrical specifications. for in depth information, along with detailed programming information, refer the psoc mixed signal array technical reference manual , which can be found on http://www.cyp ress.com/psoc . for up to date ordering, packaging, and electrical specification information, refer to the latest psoc device data sheets on the web at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at order >> buy kits at http://www.cypress.com/shop, click the online store shopping cart icon at the bottom of the web page, and click psoc (programmable system-on-chip) to view a current list of available items. technical training modules free on-demand psoc training modules are available for new users to psoc. training modules cover designing, debugging, advanced analog, and capsense. go to http://www.cypre ss.com/techtrain . consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com , click on support located at the top of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reac hed with a 4-hour guaranteed response at http://www.cypress.com/support . application notes a long list of application notes c an assist you in every aspect of your design effort. to view the psoc application notes, go to http://www.cypress.com and select application notes under documentation located in t he center of the web page. . development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on-chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. refer the psoc designer functional flow diagram ( figure 3 ). psoc designer helps the customer to select an operating configuration for psoc, write app lication code that uses the psoc, and debug the ap plication. this syst em provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. figure 3. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing information file device database importable design database device programmer graphical designer inter f ac e context sensitive help emulation pod in-circuit emulator project database application database user modules library psoc tm designer [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 5 of 37 psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration allows changing configurations at run time. psoc designer sets up power on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc bl ock configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the device data sheet. after the framework is generated, the user can add application specific code to flesh out the framework. it is also possible to change the selected components and regenerate the framework. design browser the design browser allows users to select and import preconfigured designs into the user?s project. users can easily browse a catalog of preconfigured designs to facilitate time-to-design. examples provided in the tools include a 300-baud modem, lin bus master and slave, fan controller, and magnetic card reader. application editor in the application editor you can edit c language and assembly language source code. you can also assemble, compile, link, and build. assembler . the macro assembler allows the seamless merging of the assembly code with c code. the link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler . a c language compiler that supports psoc family devices is available. even if you have never worked in the c language before, the produ ct helps you to quickly create complete c programs for the psoc family devices. the embedded, optimizing c compile r provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger s ubsystem provides hardware in-circuit emulation, which allows the designer to test the program in a physical system while providing an internal view of the psoc device. debugger co mmands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays on line context-sens itive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc through the parallel or usb port. the base unit is universal and operates with all psoc devices. em ulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in t he target board and performs full speed (24 mhz) operation designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divid ends in managing specification changes during development and by lowering inventory costs. these configurable resource s, called psoc blocks, can implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multip lexers, bus, and to the io pins. iterative development cycles permit you to adapt the hardware and the software. this substantia lly lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer integrated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. the standard user module library contains over 50 common peripherals such as adcs, dacs, timers, counters, uarts, and other uncommon peripherals, such as dtmf generators and bi -quad analog filter sections. each user module establishes th e basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pu lse width modulator user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high-level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as required. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 6 of 37 the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. pick the user modules required for your project and map them onto the psoc blocks with point-and-click simplicity. ne xt, build signal chains by interconnecting user modules to each other and the io pins. at this stage, you can also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate applicat ion? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides high-level user module api functions. figure 4. user module and source code development flows the next step is to write the ma in program, and any sub-routine using psoc designer?s applic ation editor subsystem. the application editor includes a proj ect manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional-strength ?ma kefile? system to au tomatically analyze all file dependencies and run the compiler and assembler as necessary. project-level options control optimizat ion strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 7 of 37 document conventions acronyms used the following table lists the acronyms used in this data sheet. units of measure a units of measure table is located in the section electrical specifications on page 16. table 11 on page 16 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. table 2. acronyms acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eeprom electrically erasable programmable read-only memory fsr full scale range gpio general purpose io io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter por power on reset ppor precision power on reset psoc ? programmable system-on-chip pwm pulse width modulator rom read only memory sc switched capacitor smp switch mode pump sram static random access memory [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 8 of 37 pin information this section describes, lists, and illustra tes the cy8c21x23 psoc device pins and pinou t configurations. ever y port pin (labele d with a ?p?) is capable of digital io. however, vss, vdd, smp, and xres are not capable of digital io. 8-pin part pinout 16-pin part pinout table 3. pin defi nitions - 8-pin soic pin no. type pin name description figure 5. cy8c21123 8-pin psoc device digital analog 1 io i p0[5] analog column mux input 2 io i p0[3] analog column mux input 3 io p1[1] i2c serial clock (scl), issp-sclk* 4 power vss ground connection 5 io p1[0] i2c serial data (sda), issp-sdata* 6 io i p0[2] analog column mux input 7 io i p0[4] analog column mux input 8 power vdd supply voltage legend : a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. soic 1 2 3 4 8 7 6 5 vdd p0[4], a, i p0[2], a, i p1[0], i2c sda a, i, p0[5] a, i, p0[3] i2c scl, p1[1] vss table 4. pin definitions - 16-pin soic pin no. type pin name description figure 6. cy8c21223 16-pin psoc device digital analog 1 io i p0[7] analog column mux input 2 io i p0[5] analog column mux input 3 io i p0[3] analog column mux input 4 io i p0[1] analog column mux input 5 power smp switch mode pump (smp) connection to required external components 6 power vss ground connection 7 io p1[1] i2c serial clock (scl), issp-sclk* 8 power vss ground connection 9 io p1[0] i2c serial data (sda), issp-sdata* 10 io p1[2] 11 io p1[4] optional external clock input (extclk) 12 io i p0[0] analog column mux input 13 io i p0[2] analog column mux input 14 io i p0[4] analog column mux input 15 io i p0[6] analog column mux input 16 power vdd supply voltage legend a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. soic vdd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i p1[4], extclk p1[2] p1[0], i2c sda 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, p0[7] a, i, p0[5] a, i, p0[3] a, i, p0[1] smp vss i2c scl, p1[1] vss 10 9 [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 9 of 37 table 5. pin definitions - 16-pin qfn a pin no. type pin name description figure 7. cy8c21223 16-pin psoc device digital analog 1 io i p0[3] analog column mux input 2 io i p0[1] analog column mux input 3 io p0[7] i2c serial clock (scl) 4 io p1[5] i2c serial data (sda) 5 io p1[3] 6 io p1[1] i2c serial clock (scl), issp-sclk* 7 power vss ground connection 8 io p1[0] i2c serial data (sda), issp-sdata* 9 io p1[4] optional external clock input (exclk) 10 input xres active high external reset with internal pull down 11 io i p0[0] analog column mux input 12 io i p0[4] analog column mux input 13 io i p0[6] analog column mux input 14 power vdd supply voltage 15 io i p0[7] analog column mux input 16 io i p0[5] analog column mux input legend a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. a. the center pad on the qfn package must be connected to grou nd (vss) for best mechanical, ther mal, and electrical performance. if not connected to ground, it must be electrically floated and not connected to any other signal. qfn (top view) 1 2 3 4 12 11 10 9 5 6 7 8 13 14 15 16 p0[4], ai p0[5], ai p0[7], ai pwr p0[6], ai p1[3] i2c scl, p1[1] gnd i2c sda, p1[0] p0[0], ai xres p1[4], extclk p0[3], ai p0[1], ai i2c scl, p1[7] i2c sda, p1[5] [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 10 of 37 20-pin part pinout table 6. pin defini tions - 20-pin ssop pin no. type pin name description figure 8. CY8C21323 20-pin psoc device digital analog 1 io i p0[7] analog column mux input 2 io i p0[5] analog column mux input 3 io i p0[3] analog column mux input 4 io i p0[1] analog column mux input 5 power vss ground connection 6 io p1[7] i2c serial clock (scl) 7 io p1[5] i2c serial data (sda) 8 io p1[3] 9 io p1[1] i2c serial clo ck (scl), issp-sclk* 10 power vss ground connection 11 io p1[0] i2c serial data (sda), issp-sdata* 12 io p1[2] 13 io p1[4] optional external clock input (extclk) 14 io p1[6] 15 input xres active high external reset with internal pull down 16 io i p0[0] analog column mux input 17 io i p0[2] analog column mux input 18 io i p0[4] analog column mux input 19 io i p0[6] analog column mux input 20 power vdd supply voltage legend a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. ssop vdd p0[6], a, i p0[4], a, i p0[2], a, i p0[0], a, i xres p1[6] p1[4], extclk p1[2] p1[0], i2c sda 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 a, i, p0[7] a, i, p0[5] a, i, p0[3] a, i, p0[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, p1[1] vss vss [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 11 of 37 24-pin part pinout table 7. pin definitions - 24-pin qfn* a pin no. type pin name description figure 9. CY8C21323 24-pin psoc device digital analog 1 io i p0[1] analog column mux input 2 power smp switch mode pump (smp) connection to required external components 3 power vss ground connection 4 io p1[7] i2c serial clock (scl) 5 io p1[5] i2c serial data (sda) 6 io p1[3] 7 io p1[1] i2c serial clo ck (scl), issp-sclk* 8 nc no connection 9 power vss ground connection 10 io p1[0] i2c serial data (sda), issp-sdata* 11 io p1[2] 12 io p1[4] optional external clock input (extclk) 13 io p1[6] 14 input xres active high external reset with internal pull down 15 nc no connection 16 io i p0[0] analog column mux input 17 io i p0[2] analog column mux input 18 io i p0[4] analog column mux input 19 io i p0[6] analog column mux input 20 power vdd supply voltage 21 power vss ground connection 22 io i p0[7] analog column mux input 23 io i p0[5] analog column mux input 24 io i p0[3] analog column mux input legend a = analog, i = input, and o = output. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. a. the center pad on the qfn package must be connected to grou nd (vss) for best mechanical, ther mal, and electrical performance. if not connected to ground, it must be electric ally floated and not connected to any other signal. mlf (top view ) a, i, p0[1] smp vss i2c scl, p1[7] i2c sda, p1[5] p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[4], a, i p0[2], a, i nc xr e s p1[6] 24 23 22 21 20 19 p0[3], a, i p0[5], a, i p0[7], a, i vss vdd p0[6], a, i 7 8 9 10 11 12 i2c scl, p1[1] nc vss i2c sda, p1[0] p1[2] extclk, p1[4] p0[0], a, i [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 12 of 37 register reference this section lists t he registers of the cy8c21x23 psoc device. for detailed register information, refer the psoc? mixed-signal array technical reference manual. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as io space and is divided into two banks. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. table 8. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 13 of 37 table 9. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 14 of 37 dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 9. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access blank fields are reserved and must not be accessed. # access is bit specific. table 10. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 08 48 88 c8 09 49 89 c9 0a 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 d8 19 59 99 d9 blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 15 of 37 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 10. register map bank 1 table: configuration space (continued) name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 16 of 37 electrical specifications this section presents the dc and ac electrical specifications of the cy8c21x23 psoc device. for up to date electrical specifica tions, check if you have the latest dat a sheet by visiting the web at http://www.cypress.com/psoc . specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. refer to table 25 on page 26 for the electrical specif ications on the internal main osc illator (imo) using slimo mode. the following table lists the units of me asure that are used in this section. table 11. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 figure 10. voltage versus cpu frequency figure 11. voltage versus imo frequency [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 17 of 37 absolute maximum ratings operating temperature table 12. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 ? +100 o c higher storage temperatures reduce data retention time. recommended storage temper- ature is +25c 25c. extended duration storage temperatures above 65c degrade reliability. t a ambient temperature with power applied -40 ? +85 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current in to any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch-up current ? ? 200 ma table 13. operating temperature symbol description min typ max units notes t a ambient temperature -40 ? +85 o c t j junction temperature -40 ? +100 o c the temperature rise from ambient to junction is package specific. see table 37 on page 35. the user must limit the power consumption to comply with this requirement. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 18 of 37 dc electrical characteristics dc chip-level specifications ta b l e 1 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 14. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see dc por and lvd specifica- tions, table 21 on page 22. i dd supply current, imo = 24 mhz ? 3 4 ma conditions are vdd = 5.0v, 25 o c, cpu = 3 mhz, sysclk doubler disabled. vc1 = 1.5 mhz vc2 = 93.75 khz vc3 = 0.366 khz. i dd3 supply current, imo = 6 mhz ? 1.2 2 ma conditions are vdd = 3.3v, 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz vc2 = 23.4 khz vc3 = 0.091 khz i dd27 supply current, imo = 6 mhz ? 1.1 1.5 ma conditions are vdd = 2.55v, 25 o c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz vc2 = 23.4 khz vc3 = 0.091 khz i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4 a vdd = 2.55v, 0 o c to 40 o c i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a vdd = 3.3v, -40 o c t a 85 o c v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate vdd. vdd = 3.0v to 5.25v v ref27 reference voltage (bandgap) 1.16 1.30 1.330 v trimmed for appropriate vdd. vdd = 2.4v to 3.0v agnd analog ground v ref - 0.003 v ref v ref + 0.003 v [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 19 of 37 dc general purpose io specifications ta b l e 1 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. ta b l e 1 6 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4v to 3.0v and -40 c t a 85 c. typical parameters apply to 2.7v at 25 c and are for design guidance only. table 15. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 1.0 ? ? v ioh = 10 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma, vdd = 4.75 to 5.25v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. v il input low level ? ? 0.8 v vdd = 3.0 to 5.25 v ih input high level 2.1 ? v vdd = 3.0 to 5.25 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c table 16. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull up resistor 4 5.6 8 k r pd pull down resistor 4 5.6 8 k v oh high output level vdd - 0.4 ? ? v ioh = 2.5 ma (6.25 typ), vdd = 2.4 to 3.0v (16 ma maximum, 50 ma typ combined ioh budget). v ol low output level ? ? 0.75 v iol = 10 ma, vdd = 2.4 to 3.0v (90 ma maximum combined iol budget). v il input low level ? ? 0.75 v vdd = 2.4 to 3.0 v ih input high level 2.0 ? ? v vdd = 2.4 to 3.0 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. te m p = 2 5 o c [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 20 of 37 dc amplifier specifications the following tables list the guaranteed maximum and minimum s pecifications for the voltage and te mperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 17. 5v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins ) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c v cmoa common mode voltage range 0.0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 18. 3.3v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a table 19. 2.7v dc amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absol ute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ o c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 o c v cmoa common mode voltage range 0 ? vdd - 1 v g oloa open loop gain 80 ? ? db i soa amplifier supply current ? 10 30 a [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 21 of 37 dc switch mode pump specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 20. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5v output voltage from pump 4.75 5.0 5.25 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 5.0v. v pump3v 3.3v output voltage from pump 3.00 3.25 3.60 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 3.25v. v pump2v 2.6v output voltage from pump 2.45 2.55 2.80 v configuration of footnote. a average, neglecting ripple. smp trip voltage is set to 2.55v. i pump available output current v bat = 1.8v, v pump = 5.0v v bat = 1.5v, v pump = 3.25v v bat = 1.3v, v pump = 2.55v 5 8 8 ? ? ? ? ? ? ma ma ma configuration of footnote. a smp trip voltage is set to 5.0v. smp trip voltage is set to 3.25v. smp trip voltage is set to 2.55v. v bat5v input voltage range from battery 1 .8 ? 5.0 v configuration of footnote. a smp trip voltage is set to 5.0v. v bat3v input voltage range from battery 1 .0 ? 3.3 v configuration of footnote. a smp trip voltage is set to 3.25v. v bat2v input voltage range from battery 1 .0 ? 2.8 v configuration of footnote. a smp trip voltage is set to 2.55v. v batstart minimum input voltage from battery to start pump 1.2 ? ? v configuration of footnote. a 0 o c t a 100. 1.25v at t a = -40 o c. v pump_line line regulation (over vi range) ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 21 on page 22. v pump_load load regulation ? 5 ? %v o configuration of footnote. a v o is the ?vdd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 21 on page 22. v pump_ripple output voltage ripple (depends on cap/load) ? 100 ? mvpp configuration of footnote. a load is 5 ma. a. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 12 on page 22. e 3 efficiency 35 50 ? % configuration of footnote. a load is 5 ma. smp trip voltage is set to 3.25v. e 2 efficiency 35 80 ? % for i load = 1ma, v pump = 2.55v, v bat = 1.3v, 10 uh inductor, 1 uf capacitor, and schottky diode. f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 22 of 37 figure 12. basic switch mode pump circuit dc por and lvd specifications ta b l e 2 1 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 21. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 a 2.99 b 3.09 3.20 4.55 4.75 4.83 4.95 a. always greater than 50 mv above v ppor (porlev = 00) for falling supply. b. always greater than 50 mv above v ppor (porlev = 01) for falling supply. v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 vdd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 c 3.09 3.16 3.32 d 4.74 4.83 4.92 5.12 c. always greater than 50 mv above v lvd0 . d. always greater than 50 mv above v lvd3 . v v v v v v v v battery c1 d1 + psoc t m vdd vss smp v bat v pump l 1 [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 23 of 37 dc programming specifications ta b l e 2 2 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 22. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull down resistor i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull down resistor v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operatio ns on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maxi mum cycles each (and so forth to limit the total number of c ycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the tem perature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 1,800,000 0 ? 0 ? 0 ? 0 erase/write cycles. 0 flash dr flash data retention 10 ? ? years [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 24 of 37 ac electrical characteristics ac chip-level specifications ta b l e 2 3 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 23. 5v and 3.3v ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 a,b,c mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 11 on page 16. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.75 6 6.35 a,b,c mhz trimmed for 3.3v operation using factory trim values. see figure 11 on page 16. slimo mode = 1. f cpu1 cpu frequency (5v nominal) 0.93 24 24.6 a,b a. 4.75v < vdd < 5.25v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. mhz 24 mhz only for slimo mode = 0. f cpu2 cpu frequency (3.3v nominal) 0.93 12 12.3 b, c c. 3.0v < vdd < 3.6v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-r ange operation? for information on trimming for opera- tion at 3.3v. mhz f blk5 digital psoc block frequency 0 (5v nominal) 0 48 49.2 a,b,d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz refer to the ac digital block specifications. f blk33 digital psoc block frequency (3.3v nominal) 0 24 24.6 b,d mhz f 32k1 internal low speed oscillator frequency 15 32 64 khz jitter32k 32 khz rms period jitter ? 100 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? ns t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 a,c mhz trimmed. using factory trim values. jitter24m1 24 mhz peak-to-peak period jitter (imo) ? 300 ps f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 25 of 37 figure 13. 24 mhz period jitter (imo) timing diagram figure 14. 32 khz period jitter (ilo) timing diagram table 24. 2.7v ac chip-level specifications symbol description min typ max units notes f imo12 internal main oscillator frequency for 12 mhz 11.5 12 0 12.7 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 11 on page 16. slimo mode = 1. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.35 a,b,c mhz trimmed for 2.7v operation using factory trim values. see figure 11 on page 16. slimo mode = 1. f cpu1 cpu frequency (2.7v nominal) 0.093 3 3.15 a,b mhz 24 mhz only for slimo mode = 0. f blk27 digital psoc block frequency (2.7v nominal) 0 12 12.5 a,b,c mhz refer to the ac digital block specifications. f 32k1 internal low speed oscillator frequency 8 32 96 khz jitter32k 32 khz rms period jitter ? 150 200 ns jitter32k 32 khz peak-to-peak period jitter ? 1400 ? ns t xrst external reset pulse width 10 ? ? s f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s a. 2.4v < vdd < 3.0v. b. accuracy derived from internal main oscillator with appropriate trim for vdd range. c. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on maximum frequency for user modules. jitter24m1 f 24m jitter32k f 32k1 [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 26 of 37 ac general purpose io specifications ta b l e 2 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 15. gpio timing diagram ac amplifier specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. table 25. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns vdd = 4.5 to 5.25v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns vdd = 3 to 5.25v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns vdd = 3 to 5.25v, 10% - 90% table 26. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns vdd = 2.4 to 3.0v, 10% - 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns vdd = 2.4 to 3.0v, 10% - 90% tfallf tfalls trisef tri se s 90% 10% gpio pin table 27. 5v and 3.3v ac amplifier specifications symbol description min typ max units t comp1 comparator mode response time, 50 mvpp signal centered on ref 100 ns t comp2 comparator mode response time, 2. 5v input, 0.5v overdrive 300 ns table 28. 2.7v ac amplifier specifications symbol description min typ max units t comp1 comparator mode response time, 50 mvpp signal centered on ref 600 ns t comp2 comparator mode response time, 1. 5v input, 0.5v overdrive 300 ns [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 27 of 37 ac digital block specifications ta b l e 2 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 29. 5v and 3.3v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency (> 4.75v) 49.2 mhz 4.75v < vdd < 5.25v. maximum block clocking frequency (< 4.75v) 24.6 mhz 3.0v < vdd < 4.75v. timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). ? ? ns maximum frequency, no capture ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, with or without capture ? ? 24.6 mhz counter enable pulse width 50 ? ? ns maximum frequency, no enable input ? ? 49.2 mhz 4.75v < vdd < 5.25v. maximum frequency, enable input ? ? 24.6 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 ? ? ns disable mode 50 ? ? ns maximum frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (prs mode) maximum input clock frequency ? ? 49.2 mhz 4.75v < vdd < 5.25v. crcprs (crc mode) maximum input clock frequency ? ? 24.6 mhz spim maximum input clock frequency ? ? 8.2 mhz maximum data rate at 4.1 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmissions 50 ? ? ns transmitter maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 24.6 mhz maximum data rate at 3.08 mhz due to 8 x over clocking. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 28 of 37 table 30. 2.7v ac digital block specifications function description min typ max units notes all functions maximum block clocking frequency 12.7 mhz 2.4v < vdd < 3.0v. timer capture pulse width 100 a ? ? ns maximum frequency, with or without capture ? ? 12.7 mhz counter enable pulse width 100 ? ? ns maximum frequency, no enable input ? ? 12.7 mhz maximum frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns maximum frequency ? ? 12.7 mhz crcprs (prs mode) maximum input clock frequency ? ? 12.7 mhz crcprs (crc mode) maximum input clock frequency ? ? 12.7 mhz spim maximum input clock frequency ? ? 6.35 mhz maximum data rate at 3.17 mhz due to 2 x over clocking. spis maximum input clock frequency ? ? 4.1 mhz width of ss_ negated between transmis- sions 100 ? ? ns transmitter maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. receiver maximum input clock frequency ? ? 12.7 mhz maximum data rate at 1.59 mhz due to 8 x over clocking. a. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 29 of 37 ac external clock specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75v to 5. 25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 31. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 32. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 33. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?6.06 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 12.12 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 83.4 ? 5300 ns ? low period with cpu clock divide by 1 83.4 ? ?ns ? power up imo to switch 150 ? ? s [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 30 of 37 ac programming specifications ta b l e 3 4 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, or 3.0v to 3.6v and -40 c t a 85 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. ac i 2 c specifications ta b l e 3 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -40 c t a 85 c, 3.0v to 3.6v and -40 c t a 85 c, or 2.4v to 3.0v and -40 c t a 85 c, respectively. typica l parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 34. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0 table 35. ac characteristics of the i 2 c sda and scl pins for vcc 3.0v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 0 250 0 ? 0 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this automatically becomes the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2 c-bus specification) before the scl line is released. ? 0 ns 0 t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are su ppressed by the input filter. ? ?050ns [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 31 of 37 figure 16. definition for timing for fast/standard mode on the i 2 c bus table 36. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ? ? khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c setup time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are su ppressed by the input filter. ? ???ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 32 of 37 packaging information this section illustrates the packaging specifications for the cy8c21x23 psoc device, along with the thermal impedances for each package and minimum solder reflow peak temperature. important note emulation tools may require a larger ar ea on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . packaging dimensions figure 17. 8-pin (150-mil) soic seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 51-85066 *c [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 33 of 37 figure 18. 16-pin (150-mil) soic figure 19. 16-pin col 51-85022 *b 001-09116 *d [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 34 of 37 figure 20. 20-pin (210-mil) ssop figure 21. 24-pin (4x4) qfn important note for information on the preferred dimensions for mount ing qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . it is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin qfn psoc devices. 51-85077 *c top view c 1.00 max. n bottom view seating plane n 2 2 0.230.05 0.50 1 1 0.05 0-12 0.30-0.50 2.45 0.05 max. c 0.80 max. 0.20 ref. pin1 id 0.45 0.20 r. side view 3.90 4.10 3.70 3.80 4.10 3.70 3.80 3.90 0.420.18 2.55 2.55 2.45 (4x) 2.49 2.49 5. package code ly24a lf24a part # description lead free standard 2. reference jedec#: mo-220 4. all dimensions are in mm [min/max] 1. hatch is solderable exposed metal. 3. package weight: 0.042g notes : ?0.50 solderable exposed pad 51-85203 *a [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 35 of 37 thermal impedances solder reflow peak temperature ta b l e 3 8 lists the minimum solder reflow peak temperature to achieve good solderability. table 37. thermal impedances per package package typical ja * 8 soic 186 o c/w 16 soic 125 o c/w 16 qfn 46 c/w 20 ssop 117 o c/w 24 mlf** 40 o c/w * t j = t a + power x ja **to achieve the thermal impedance specifi ed for the qfn package, the center thermal pad must be soldered to the pcb ground plane. table 38. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 8 soic 240 o c 260 o c 16 soic 240 o c 260 o c 16 qfn 240 o c 260 o c 20 ssop 240 o c 260 o c 24 mlf 240 o c 260 o c *higher temperatures may be required based on the solder me lting point. typical temperatures for solder are 220+/-5 o c with sn-pb or 245+/-5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback [+] feedback
cy8c21123, cy8c21223, CY8C21323 document number: 38-12022 rev. *h page 36 of 37 ordering information the following table lists the cy8c21x23 psoc device?s key package features and ordering codes. ordering code definitions table 39. cy8c21x23 psoc device key features and ordering information package ordering code flash (bytes) ram (bytes) switch mode pump temperature range digital psoc blocks analog blocks digital io pins analog inputs analog outputs xres pin 8-pin (150-mil) soic cy8c21123-24sxi 4k 256 no -40c to +85c 4 4 6 4 0 no 8-pin (150-mil) soic (tape and reel) cy8c21123-24sxit 4k 256 no -40c to +85c 4 4 6 4 0 no 16-pin (150-mil) soic cy8c21223-24sxi 4k 256 yes -40c to +85c 4 4 12 8 0 no 16-pin (150-mil) soic (tape and reel) cy8c21223-24sxit 4k 256 yes -40c to +85c 4 4 12 8 0 no 16-pin (3x3) qfn cy8c21223-lgxi 4k 256 yes -40c to +85c 4 4 12 8 0 no 20-pin (210-mil) ssop CY8C21323-24pvxi 4k 256 no -40c to +85c 4 4 16 8 0 yes 20-pin (210-mil) ssop (tape and reel) CY8C21323-24pvxit 4k 256 no -40c to +85c 4 4 16 8 0 yes 24-pin (4x4) qfn CY8C21323-24lfxi 4k 256 yes -40c to +85c 4 4 16 8 0 yes 24-pin (4x4) qfn (tape and reel) CY8C21323-24lfxit 4k 256 yes -40c to +85c 4 4 16 8 0 yes cy 8 c 21 xxx-24xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx = qfn pb-free ax = tqfp pb-free speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = cypress semiconductor company id: cy = cypress [+] feedback [+] feedback
document number: 38-12022 rev. *h revised october 22, 2008 page 37 of 37 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublic ensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. cy8c21123, cy8c 21223, CY8C21323 ? cypress semiconductor corporation, 2004-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy8c21123/cy8c21223/CY8C21323 psoc ? mixed signal array document number:38-12022 revision ecn orig. of change submission date description of change ** 133248 nwj see ecn new silicon and document (revision **). *a 208900 nwj see ecn add new part, new package and update all ordering codes to pb-free. *b 212081 nwj see ecn expand and prepare preliminary version. *c 227321 cms team see ecn update specs., data, format. *d 235973 sfv see ecn updated overview and electrical spec. c hapters, along with 24 -pin pinout. added cmp_go_en register (1, 64h) to mapping table. *e 290991 hmt see ecn update data sheet standards per sfv memo. fix device table. add part numbers to pinouts and fine tune. change 20-pin ssop to CY8C21323. add reflow temp. table. update diagrams and specs. *f 301636 hmt see ecn dc chip-level specification changes. update links to new cy.com portal. *g 324073 hmt see ecn obtained clearer 16 soic package. update thermal impedances and solder reflow tables. re-add pinout issp nota tion. fix adc type-o. fix tmp register names. update electrical specifications. add cy logo. update cy copyright. make data sheet final. *h 2588457 ket/hmi/ aesa 10/22/2008 new package information on page 9. converted data sheet to new template. added 16-pin ofn package diagram. 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